'Synopsys' donation of these additional checkers to become part of the OVL industry-standard library is to be applauded.' 'We are certainly in favor of assertion checkers, as they help SoC designers to complete their verification work more quickly,' said Mike Turpin, chair of Accellera's OVL Technical Subcommittee and principal validation engineer at ARM. These checkers can be used with designs expressed in SystemVerilog, Verilog, VHDL, or mixed-language RTL.

This reduces hours or days of effort down to a simple five-minute task to instantiate the checker. For example, an engineer can simply connect the 'assert_arbiter' checker directly to the request and grant lines of an arbiter, without having to consider which specific assertions and functional coverage points might be appropriate for arbitration logic. They are easy to use because they correspond directly to widely-used design elements such as arbiters, FIFOs, memories, registers, and handshake interfaces. These checkers are used by designers and verification engineers to capture key attributes of their RTL designs. The donated library contains 20 unique assertion checkers, entirely complementary to Accellera's current OVL of assertion monitors. 'Synopsys' donation to Accellera puts these proven checkers on a path to become an industry standard so that even more design and verification teams can achieve similar productivity benefits.' 'As the SystemVerilog leader, Synopsys has provided its customers with advanced assertion checkers for several years to enable higher designer productivity and faster adoption of assertion-based verification,' said Manoj Gandhi, senior vice president and general manager of the Verification Group at Synopsys, Inc. In addition, extensive functional coverage information within each checker has provided them with automatic enhancements to existing coverage metrics, fostering a more predictable verification process.

Provided as SystemVerilog source code, the checkers included in this library have been widely used by design and verification engineers for the past few years to add SystemVerilog assertions (SVA) to their designs more quickly and more easily, enhancing engineering productivity.

(NASDAQ: SNPS), a world leader in semiconductor design software, today announced that it has donated a library of advanced SystemVerilog assertion checkers defined in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog to Accellera, the electronic design automation (EDA) organization focused on EDA standards.

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